1. Field of the Invention
The present invention relates to a shift register and an image display apparatus using the same. More specifically, the present invention relates to a shift register where latch circuits constituting the shift register are divided into a plurality of circuit blocks and a clock signal is selectively supplied only to latch circuits in a circuit block which is currently transferring a digital signal, and an active matrix image display apparatus using such a shift register for its data signal line driver and the like.
2. Description of the Related Art
Shift registers have been widely used in various types of electronic apparatuses. Hereinbelow, a conventional shift register with a large number of stages which is used for a driver of an image display apparatus will be specifically described.
FIG. 18 schematically shows a conventional active matrix liquid crystal display apparatus. A liquid crystal display apparatus 200 includes a liquid crystal panel 31, a data signal line driver 32, and a scanning signal line driver 33. The liquid crystal panel 31 includes a pair of transparent substrates made of glass or the like disposed to face each other with liquid crystal interposed therebetween. On one of the transparent substrates, M data signal lines SL.sub.1 to SL.sub.M run in one direction and N scanning signal lines GL.sub.1 to GL.sub.N run in a direction perpendicular to the direction of the data signal lines SL.sub.1 to SL.sub.M. At the crossing of each data signal line SL.sub.i (1.ltoreq.i.ltoreq.M; i is an integer) and each scanning signal line GL.sub.j (1.ltoreq.j.ltoreq.N; j is an integer), a pixel PIX.sub.i,j is formed.
The data signal line driver 32 samples a data signal DAT based on a data clock signal CKS and a data start signal SPS, and distributes the sampled signal to the data signal lines SL.sub.1 to SL.sub.M. The scanning signal line driver 33 scans the scanning signal lines GL.sub.1 to GL.sub.N one by one sequentially based on a scanning clock signal CKG and a scanning start signal SPG and selects a row of pixels PIX.sub.1,j to PIX.sub.M,j in which the data signal DAT supplied to the data signal lines SL.sub.1 to SL.sub.M should be written.
Referring to FIG. 19, the data signal line driver 32 supplies the data signal DAT to the data signal line SL.sub.i by a point sequential driving method or a line sequential driving method. In the point sequential driving method, the data signal DAT is supplied to the data signal line SL.sub.i whenever it is sampled. In the line sequential driving method, the data signal DAT is sequentially sampled for one horizontal scanning period and held, and the sampled sequential data signal DAT corresponding to one line is supplied to the data signal lines SL.sub.1 to SL.sub.M at one time. The data signal line driver 32 of either of the above driving methods uses a shift register. Hereinbelow, the data signal line driver of the point sequential driving method where the circuit configuration is simpler will be described.
Referring to FIG. 19, the data signal line driver 32 includes a shift register 34 composed of M latch circuits LT.sub.1 to LT.sub.M. The shift register 34 sequentially transfers the data start signal SPS through the latch circuits LT.sub.1 to LT.sub.M in synchronization with the data clock signal CKS. The data start signal SPS is a pulse signal which includes a pulse every horizontal scanning period. The data start signal SPS is output from the latch circuits LT.sub.1 to LT.sub.M as parallel latch signals to control terminals of corresponding sampling switches ASW.sub.1 to ASW.sub.M via corresponding buffer circuits BUF.sub.1 to BUF.sub.M. Each buffer circuit BUF.sub.i amplifies, and if required inverts, the data start signal SPS held in the latch circuit LT.sub.i. Each sampling switch ASW.sub.i is an analog switch which turns on/off the circuit depending on the input at the control terminal thereof. The data signal DAT is supplied to the data signal lines SL.sub.1 to SL.sub.M through the sampling switches ASW.sub.1 to ASW.sub.M. Thus, in the data signal line driver 32, the pulse of the data start signal SPS is sequentially transferred through the latch circuits LT.sub.1 to LT.sub.M of the shift register 34 every horizontal scanning period to sequentially turn on the corresponding sampling switches ASW.sub.1 to ASW.sub.M, so that the data signal DAT is sampled and supplied to the corresponding data signal lines SL.sub.1 to SL.sub.M.
The scanning signal line driver 33 can be realized by using a shift register or a combination of a counter and a decoder. A shift register is often used because the circuit configuration is simpler and the number of transistors required is smaller. Hereinbelow, the scanning signal line driver using a shift register will be described.
Referring to FIG. 20, the scanning signal line driver 33 includes a shift register 35 composed of N latch circuits LT.sub.1 to LT.sub.N. The shift register 35 sequentially transfers the scanning start signal SPG through the latch circuits LT.sub.1 to LT.sub.N in synchronization with the scanning clock signal CKG. The scanning start signal SPG is a pulse signal which includes a pulse every vertical scanning period. The scanning start signal SPG is output from the latch circuits LT.sub.1 to LT.sub.N as parallel latch signals to corresponding logic gates LOG.sub.1 to LOG.sub.N via corresponding first buffer circuits BUF.sub.1,1 to BUF.sub.1,N. The logic gates LOG.sub.1 to LOG.sub.N also receive a scanning control signal GPS for controlling the scanning. The outputs of the logic gates LOG.sub.1 to LOG.sub.N are connected to the corresponding scanning signal lines GL.sub.1 to GL.sub.N via corresponding second buffer circuits BUF.sub.2,1 to BUF.sub.2,N. Thus, in the scanning signal line driver 33, the pulse of the scanning start signal SPG is sequentially transferred through the latch circuits LT.sub.1 to LT.sub.N of the shift register 35 every vertical scanning period to sequentially activate the corresponding scanning signal lines GL.sub.1 to GL.sub.N.
Referring to FIG. 21, the pixel PIX.sub.i,j formed at the crossing of the data signal line SL.sub.i and the scanning signal line GL.sub.j in the liquid crystal panel 31 includes a switching element SW and a pixel capacitance composed of a liquid crystal (LC) capacitor C.sub.l and a storage capacitor C.sub.s. The switching element SW is a thin film transistor (TFT) of a MOSFET type formed on one of the transparent substrates. The gate of the switching element SW is connected with the scanning signal line GL.sub.j. The LC capacitor C.sub.l is formed between a pixel electrode of the pixel PIX.sub.i,j formed on one of the transparent substrates and a common electrode formed on the other transparent substrate via the liquid crystal. The storage capacitor C.sub.s is formed as required to supplement charges stored in the LC capacitor C.sub.l. One electrode of the storage capacitor C.sub.s is formed on one of the transparent substrates. The pixel electrode of the LC capacitor C.sub.l and this electrode of the storage capacitor C.sub.s are connected with the data signal line SL.sub.i via the source-drain of the switching element SW. With this configuration, when the scanning signal line GL.sub.j is made active by the scanning of the scanning signal line driver 33, the switching elements SW of the pixels PIX.sub.1,j to PIX.sub.M,j corresponding to the scanning signal line GL.sub.j are turned on, allowing the data signal DAT supplied to the data signal lines SL.sub.1 to SL.sub.M from the data signal line driver 32 to be written in the LC capacitors C.sub.l and the storage capacitors C.sub.s of the pixels PIX.sub.1,j to PIX.sub.M,j. Thus, the applied voltage at the LC capacitor C.sub.l of the pixel PIX.sub.i,j changes depending on the data signal DAT written in the LC capacitor C.sub.l. This makes it possible to control the transmittance and reflectance of the liquid crystal at the pixel PIX.sub.i,j. In this way, the liquid crystal display apparatus 200 (FIG. 18) can realize image display with N.times.M pixels.
The shift registers 34 and 35 used in the data signal line driver 32 and the scanning signal line driver 33 of the conventional liquid crystal display apparatus will be described more specifically.
Referring to FIG. 22, in the shift register 34 or 35, a start signal ST (the data start signal SPS or the scanning start signal SPG) is sequentially transferred through the latch circuits LT.sub.1 to LT.sub.K (K stages in this example) based on not only a clock signal CLK (the data clock signal CKS or the scanning clock signal CKG) but also a clock signal CLK bar obtained by inverting the clock signal CLK, to obtain output signals OUT.sub.1 to OUT.sub.K.
FIG. 23 shows a specific example of two adjacent latch circuits LT.sub.k and LT.sub.k+1 (1.ltoreq.k.ltoreq.K; k is an odd number) of the shift register 34 or 35 (FIG. 22). The preceding latch circuit LT.sub.k includes one inverter 1 and two clocked inverters 2 and 3, while the subsequent latch circuit LT.sub.k+1 includes one inverter 4 and two clocked inverters 5 and 6. Each of the clocked inverters 2, 3, 5, and 6 is a 3-state buffer which serves as a normal inverter when the input at the control terminal thereof is active but outputs high impedance when it is inactive. In the latch circuit LT.sub.k or LT.sub.k+1, the inverter 1 or 4 and the clocked inverter 2 or 5 are connected to form a loop, constituting a flipflop circuit. The start signal ST is input into the other clocked inverter 3 or 6 and transferred to the next stage via the inverter 1 or 4. The output signal OUT.sub.k or OUT.sub.k+1 is obtained from the output of the clocked inverter 3 or 6. The clock signal CLK is supplied to the control terminal of the clocked inverter 3 of the preceding latch circuit LT.sub.k and the control terminal of the clocked inverter 5 of the subsequent latch circuit LT.sub.k+1. The inverted clock signal CLK bar is supplied to the control terminal of the clocked inverter 2 of the preceding latch circuit LT.sub.k and the control terminal of the clocked inverter 6 of the subsequent latch circuit LT.sub.k+1.
In the latch circuits LT.sub.k and LT.sub.k+1 with the above configuration, when the clock signal CLK becomes active, the preceding latch circuit LT.sub.k receives the start signal ST via the clocked inverter 3, while the subsequent latch circuit LT.sub.k+1 shuts off the input to hold the start signal ST which had been input until immediately before the shutoff in the flipflop circuit composed of the inverter 4 and the clocked inverter 5. When the inverted clock signal CLK bar becomes active in the next half cycle, the preceding latch circuit LT.sub.k shuts off the input to hold the start signal ST which had been input until immediately before the shutoff in the flipflop circuit composed of the inverter 1 and the clocked inverter 2, while the subsequent latch circuit LT.sub.k+1 receives the start signal ST output from the preceding latch circuit LT.sub.k via the clocked inverter 6. Thus, the latch circuits LT.sub.k and LT.sub.k+1 sequentially latch the start signal ST received from the preceding latch circuit and transfer the latched signal to the subsequent latch circuit in response to the rising and falling of the clock signal CLK.
The shift register 34 or 35 transfers only one pulse every horizontal scanning period or every vertical scanning period. Accordingly, the power consumption required for the transfer of the start signal ST (power consumption with respect to a power terminal) is not so large. However, the clock signals CLK and CLK bar are input into the control terminals of the clocked inverters 2, 3, 5, and 6 of the latch circuits LT.sub.k and LT.sub.k+1, changing the signal levels repeatedly within one horizontal scanning period and one vertical scanning period. Moreover, the number of stages (latch circuits) of the shift register 34 or 35 used in a display apparatus is very large as described above. For example, in the 640.times.480 dot VGA (video graphics array) standard, 640 stages are required for the data signal line driver 32 while 480 stages for the scanning signal line driver 33. In the 1024.times.768 dot XGA (extended graphics array) standard, 1024 stages are required for the data signal line driver 32 while 768 stages for the scanning signal line driver 33.
In the conventional shift register 34 or 35, therefore, a large amount of current flows to charge or discharge parasitic capacitances of signal lines for the clock signal CLK and gate capacitances of the clocked inverters 2, 3, 5, and 6. This undesirably increases the power consumption.
In the above-described conventional active matrix liquid crystal display apparatus, the switching element SW of the pixel PIX.sub.i,j is often a TFT made of amorphous silicon formed on one of the transparent substrates of the liquid crystal panel 31. In this case, the data signal line driver 32 and the scanning signal line driver 33 are provided as external integrated circuits (ICs). However, with the recent trend towards a larger screen size of the liquid crystal display apparatus, there is a need for cost reduction for the ICs of the data signal line driver 32 and the scanning signal line driver 33, improvement of the reliability at the mounting of such ICs, and the like. To meet these needs, a technique of integrally forming the drivers 32 and 33 on the transparent substrate of the liquid crystal panel 31 has been developed. According to this technique, TFTs including a polysilicon layer formed on a substrate made of a heat-resistant, transparent material such as silica glass are used as transistors for the drivers 32 and 33 as well as the switching element SW of the pixel PIX.sub.i,j. Another approach has been studied where polysilicon TFTs are formed on a glass substrate at a process temperature below a glass distortion point (about 60.degree. C.). FIG. 24 shows a configuration of a liquid crystal display apparatus employing this approach. A liquid crystal display apparatus 300 includes a data signal line driver 32a and a scanning signal line driver 33a monolithically formed on a transparent substrate of a liquid crystal display panel 31 together with pixels PIX.sub.1,1 to PIX.sub.M,N, data signal lines SL.sub.1 to SL.sub.M, and scanning signal lines GL.sub.1 to GL.sub.N. Only a timing signal generation circuit 36 and a power voltage generation circuit 37 are provided externally. When polysilicon TFTs are used as in this case, the above-described point sequential driving method where the circuit configuration is simpler is often employed for the data signal line driving circuit 32a.
However, polysilicon TFTs have inferior device characteristics compared with single crystalline silicon transistors of normal ICs formed on a single crystalline silicon substrate. A large device size is therefore required, and this increases the gate capacitances. Accordingly, if the conventional shift registers 34 and 35 (FIG. 22) are used for the data signal line driver 32a and the scanning signal line driver 33a, the gate capacitances of the clocked inverters 2, 3, 5, and 6 increase. This undesirably results in further increasing the power consumption.
In order to overcome the above problem, Japanese Patent Publication No. 63-50717 and Japanese Laid-Open Patent Publication No. 63-271298 disclose techniques where a shift register is divided into a plurality of circuit blocks to supply a clock signal only to a circuit block which is currently transferring a pulse of a start signal to suppress the increase in the power consumption caused by the clock signal.
More specifically, according to th e technique disclosed in the Japanese Patent Publication No. 63-50717, a start signal is transferred through a shift register for selection having stages corresponding to the number of circuit blocks obtained by dividing an original shift register in synchronization with a clock signal processed by a frequency divider, so that only a circuit block requiring the clock signal can be sequentially selected. This publication also discloses a technique where the circuit block is selected by a counter for counting the clock signal and a decoder for decoding the output of the counter. However, these techniques additionally require the frequency divider and the shift register for selection or the counter and the decoder for selecting the circuit block, causing another problem of increasing the circuit size and complexity.
According to the technique disclosed in the Japanese Laid-Open Patent Publication No. 63-271298, the timing when a clock signal is supplied to each circuit block obtained by dividing a shift register is determined based on the transferred signal output from the preceding circuit block, while the timing when the supply of the clock signal is terminated is determined based on the transferred signal output from itself. However, this technique additionally requires circuits for determining the timings when the supply of the clock signal is initiated and terminated, causing another problem of increasing the circuit size.